Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices

L. Manchanda, G. R. Weber, W. Mansfield, D. M. Boulin, K. Krisch, Y. O. Kim, R. Storz, N. Moriya, H. S. Luftman, Leonard C Feldman, M. L. Green, R. C. Kistler, J. T C Lee, F. Klemens

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We report the fabrication and device characteristics of a 50Angstrom thick dual-layer gate dielectric with high interface quality (Dit and Qf APEQ1010/cm2) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a APEQ40Angstrom thick oxynitride layer, through which slow O2 diffusion is used to grow a APEQ10Angstrom thick SiO2 at the interface. The small thickness of the SiO2 layer reduce the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO2 layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950°C.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting
Editors Anon
PublisherPubl by IEEE
Pages459-462
Number of pages4
ISBN (Print)0780314506
Publication statusPublished - 1993
EventProceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA
Duration: Dec 5 1993Dec 8 1993

Other

OtherProceedings of the 1993 IEEE International Electron Devices Meeting
CityWashington, DC, USA
Period12/5/9312/8/93

Fingerprint

Boron
Gate dielectrics
Chemical vapor deposition
Fabrication
Oxidation
Temperature
Hot Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Manchanda, L., Weber, G. R., Mansfield, W., Boulin, D. M., Krisch, K., Kim, Y. O., ... Klemens, F. (1993). Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices. In Anon (Ed.), Technical Digest - International Electron Devices Meeting (pp. 459-462). Publ by IEEE.

Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices. / Manchanda, L.; Weber, G. R.; Mansfield, W.; Boulin, D. M.; Krisch, K.; Kim, Y. O.; Storz, R.; Moriya, N.; Luftman, H. S.; Feldman, Leonard C; Green, M. L.; Kistler, R. C.; Lee, J. T C; Klemens, F.

Technical Digest - International Electron Devices Meeting. ed. / Anon. Publ by IEEE, 1993. p. 459-462.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Manchanda, L, Weber, GR, Mansfield, W, Boulin, DM, Krisch, K, Kim, YO, Storz, R, Moriya, N, Luftman, HS, Feldman, LC, Green, ML, Kistler, RC, Lee, JTC & Klemens, F 1993, Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices. in Anon (ed.), Technical Digest - International Electron Devices Meeting. Publ by IEEE, pp. 459-462, Proceedings of the 1993 IEEE International Electron Devices Meeting, Washington, DC, USA, 12/5/93.
Manchanda L, Weber GR, Mansfield W, Boulin DM, Krisch K, Kim YO et al. Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices. In Anon, editor, Technical Digest - International Electron Devices Meeting. Publ by IEEE. 1993. p. 459-462
Manchanda, L. ; Weber, G. R. ; Mansfield, W. ; Boulin, D. M. ; Krisch, K. ; Kim, Y. O. ; Storz, R. ; Moriya, N. ; Luftman, H. S. ; Feldman, Leonard C ; Green, M. L. ; Kistler, R. C. ; Lee, J. T C ; Klemens, F. / Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices. Technical Digest - International Electron Devices Meeting. editor / Anon. Publ by IEEE, 1993. pp. 459-462
@inproceedings{fbfde2dbed0647ba9c4cabe5492d703d,
title = "Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices",
abstract = "We report the fabrication and device characteristics of a 50Angstrom thick dual-layer gate dielectric with high interface quality (Dit and Qf APEQ1010/cm2) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a APEQ40Angstrom thick oxynitride layer, through which slow O2 diffusion is used to grow a APEQ10Angstrom thick SiO2 at the interface. The small thickness of the SiO2 layer reduce the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO2 layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950°C.",
author = "L. Manchanda and Weber, {G. R.} and W. Mansfield and Boulin, {D. M.} and K. Krisch and Kim, {Y. O.} and R. Storz and N. Moriya and Luftman, {H. S.} and Feldman, {Leonard C} and Green, {M. L.} and Kistler, {R. C.} and Lee, {J. T C} and F. Klemens",
year = "1993",
language = "English",
isbn = "0780314506",
pages = "459--462",
editor = "Anon",
booktitle = "Technical Digest - International Electron Devices Meeting",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices

AU - Manchanda, L.

AU - Weber, G. R.

AU - Mansfield, W.

AU - Boulin, D. M.

AU - Krisch, K.

AU - Kim, Y. O.

AU - Storz, R.

AU - Moriya, N.

AU - Luftman, H. S.

AU - Feldman, Leonard C

AU - Green, M. L.

AU - Kistler, R. C.

AU - Lee, J. T C

AU - Klemens, F.

PY - 1993

Y1 - 1993

N2 - We report the fabrication and device characteristics of a 50Angstrom thick dual-layer gate dielectric with high interface quality (Dit and Qf APEQ1010/cm2) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a APEQ40Angstrom thick oxynitride layer, through which slow O2 diffusion is used to grow a APEQ10Angstrom thick SiO2 at the interface. The small thickness of the SiO2 layer reduce the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO2 layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950°C.

AB - We report the fabrication and device characteristics of a 50Angstrom thick dual-layer gate dielectric with high interface quality (Dit and Qf APEQ1010/cm2) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a APEQ40Angstrom thick oxynitride layer, through which slow O2 diffusion is used to grow a APEQ10Angstrom thick SiO2 at the interface. The small thickness of the SiO2 layer reduce the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO2 layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950°C.

UR - http://www.scopus.com/inward/record.url?scp=0027879118&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027879118&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0027879118

SN - 0780314506

SP - 459

EP - 462

BT - Technical Digest - International Electron Devices Meeting

A2 - Anon, null

PB - Publ by IEEE

ER -