We report the fabrication and device characteristics of a 50Angstrom thick dual-layer gate dielectric with high interface quality (Dit and QfAPEQ1010/cm2) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a APEQ40Angstrom thick oxynitride layer, through which slow O2 diffusion is used to grow a APEQ10Angstrom thick SiO2 at the interface. The small thickness of the SiO2 layer reduce the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO2 layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950°C.