Abstract
We report the fabrication and device characteristics of a 50Angstrom thick dual-layer gate dielectric with high interface quality (Dit and Qf APEQ1010/cm2) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a APEQ40Angstrom thick oxynitride layer, through which slow O2 diffusion is used to grow a APEQ10Angstrom thick SiO2 at the interface. The small thickness of the SiO2 layer reduce the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO2 layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950°C.
| Original language | English |
|---|---|
| Title of host publication | Technical Digest - International Electron Devices Meeting |
| Editors | Anon |
| Publisher | Publ by IEEE |
| Pages | 459-462 |
| Number of pages | 4 |
| ISBN (Print) | 0780314506 |
| Publication status | Published - 1993 |
| Event | Proceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA Duration: Dec 5 1993 → Dec 8 1993 |
Other
| Other | Proceedings of the 1993 IEEE International Electron Devices Meeting |
|---|---|
| City | Washington, DC, USA |
| Period | 12/5/93 → 12/8/93 |
Fingerprint
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices. / Manchanda, L.; Weber, G. R.; Mansfield, W.; Boulin, D. M.; Krisch, K.; Kim, Y. O.; Storz, R.; Moriya, N.; Luftman, H. S.; Feldman, Leonard C; Green, M. L.; Kistler, R. C.; Lee, J. T C; Klemens, F.
Technical Digest - International Electron Devices Meeting. ed. / Anon. Publ by IEEE, 1993. p. 459-462.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Boron-retarding and high interface quality thin fate dielectric for deep-submicron devices
AU - Manchanda, L.
AU - Weber, G. R.
AU - Mansfield, W.
AU - Boulin, D. M.
AU - Krisch, K.
AU - Kim, Y. O.
AU - Storz, R.
AU - Moriya, N.
AU - Luftman, H. S.
AU - Feldman, Leonard C
AU - Green, M. L.
AU - Kistler, R. C.
AU - Lee, J. T C
AU - Klemens, F.
PY - 1993
Y1 - 1993
N2 - We report the fabrication and device characteristics of a 50Angstrom thick dual-layer gate dielectric with high interface quality (Dit and Qf APEQ1010/cm2) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a APEQ40Angstrom thick oxynitride layer, through which slow O2 diffusion is used to grow a APEQ10Angstrom thick SiO2 at the interface. The small thickness of the SiO2 layer reduce the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO2 layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950°C.
AB - We report the fabrication and device characteristics of a 50Angstrom thick dual-layer gate dielectric with high interface quality (Dit and Qf APEQ1010/cm2) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a APEQ40Angstrom thick oxynitride layer, through which slow O2 diffusion is used to grow a APEQ10Angstrom thick SiO2 at the interface. The small thickness of the SiO2 layer reduce the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO2 layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950°C.
UR - http://www.scopus.com/inward/record.url?scp=0027879118&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0027879118&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027879118
SN - 0780314506
SP - 459
EP - 462
BT - Technical Digest - International Electron Devices Meeting
A2 - Anon, null
PB - Publ by IEEE
ER -