The thickness of silicon dioxide that is used as the transistor gate dielectric in most advanced memory and logic applications has decreased below 7 nm. Unfortunately, the accuracy and reproducibility of metrology used to measure gate dielectric thickness during manufacture of integrated circuits remains in some dispute. In addition, detailed materials characterization studies have resulted in a variety of descriptions for the oxide-interface-substrate system. Part of the problem is that each method measures a different quantity. Another related issue concerns how one should define and model the critical dielectric/substrate interface. As scaling continues, the interface between silicon dioxide and silicon becomes a larger part of the total thickness of the oxide film. Although materials characterization studies have focused on this interface, there have been few attempts to compare the results of these methods based on an understanding of the models used to interpret the data. In this review, we describe the physical and electrical characterization of the interfacial layer. Infrared absorption data are reviewed and previous interpretations of the LO/TO phonon shifts as a function of oxide thickness are refined. We correlate the available results between physical methods and between physical and electrical methods. This information is essential to inclusion of an interfacial layer in optical models used to measure silicon dioxide inside the clean room. We also describe some characterization issues for nitrided oxides.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials