Gate-tunable memristors from monolayer MoS2

Vinod K. Sangwan; Hong Sub Lee; Mark C. Hersam

doi:10.1109/IEDM.2017.8268330

Gate-tunable memristors from monolayer MoS₂

Vinod K. Sangwan, Hong Sub Lee, Mark C. Hersam

Northwestern University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We report here gate-tunable memristors based on monolayer MoS2 grown by chemical vapor deposition (CVD). These memristors are fabricated in a field-effect geometry with the channel consisting of poly crystalline MoS2 films with grain sizes of 3-5 μm. The device characteristics show switching ratios up to ∼500, with the resistance in individual states being continuously gate-tunable by over three orders of magnitude. The resistive switching results from dynamically varying threshold voltage and Schottky barrier heights, whose underlying physical mechanism appears to be vacancy migration and/or charge trapping. Top-gated devices achieve reversible tuning of threshold voltage, with potential utility in non-volatile memory or neuromorphic architectures.

Original language	English
Title of host publication	2017 IEEE International Electron Devices Meeting, IEDM 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	5.1.1-5.1.4
ISBN (Electronic)	9781538635599
DOIs	https://doi.org/10.1109/IEDM.2017.8268330
Publication status	Published - Jan 23 2018
Event	63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States Duration: Dec 2 2017 → Dec 6 2017

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	63rd IEEE International Electron Devices Meeting, IEDM 2017
Country	United States
City	San Francisco
Period	12/2/17 → 12/6/17

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ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

Sangwan, V. K., Lee, H. S., & Hersam, M. C. (2018). Gate-tunable memristors from monolayer MoS₂. In 2017 IEEE International Electron Devices Meeting, IEDM 2017 (pp. 5.1.1-5.1.4). (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2017.8268330

Gate-tunable memristors from monolayer MoS₂. / Sangwan, Vinod K.; Lee, Hong Sub; Hersam, Mark C.

2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 5.1.1-5.1.4 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sangwan, VK, Lee, HS & Hersam, MC 2018, Gate-tunable memristors from monolayer MoS₂. in 2017 IEEE International Electron Devices Meeting, IEDM 2017. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., pp. 5.1.1-5.1.4, 63rd IEEE International Electron Devices Meeting, IEDM 2017, San Francisco, United States, 12/2/17. https://doi.org/10.1109/IEDM.2017.8268330

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Access to Document

10.1109/IEDM.2017.8268330