Phosphorous passivation of the SiO 2/4H-SiC interface

Y. K. Sharma, A. C. Ahyi, T. Issacs-Smith, X. Shen, S. T. Pantelides, X. Zhu, L. C. Feldman, J. Rozen, J. R. Williams

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48 Citations (Scopus)

Abstract

We describe experimental and theoretical studies to determine the effects of phosphorous as a passivating agent for the SiO 2/4H-SiC interface. Annealing in a P 2O 5 ambient converts the SiO 2 layer to PSG (phosphosilicate glass) which is known to be a polar material. Higher mobility (approximately twice the value of 30-40 cm 2/V s obtained using nitrogen introduced with an anneal in nitric oxide) and lower threshold voltage are compatible with a lower interface defect density. Trap density, current-voltage and bias-temperature stress (BTS) measurements for MOS capacitors are also discussed. The BTS measurements point to the possibility of an unstable MOSFET threshold voltage caused by PSG polarization charge at the O-S interface. Theoretical considerations suggest that threefold carbon atoms at the interface can be passivated by phosphorous which leads to a lower interface trap density and a higher effective mobility for electrons in the channel. The roles of phosphorous in the passivation of correlated carbon dangling bonds, for SiC counter-doping, for interface band-tail state suppression, for Na-like impurity band formation and for substrate trap passivation are also discussed briefly.

Original languageEnglish
Pages (from-to)103-107
Number of pages5
JournalSolid-State Electronics
Volume68
DOIs
Publication statusPublished - Feb 1 2012

Keywords

  • Channel mobility
  • Interface trap density
  • Phosphorous
  • Threshold voltage stability

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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  • Cite this

    Sharma, Y. K., Ahyi, A. C., Issacs-Smith, T., Shen, X., Pantelides, S. T., Zhu, X., Feldman, L. C., Rozen, J., & Williams, J. R. (2012). Phosphorous passivation of the SiO 2/4H-SiC interface. Solid-State Electronics, 68, 103-107. https://doi.org/10.1016/j.sse.2011.10.030