Reduced graphene oxide electrodes for large area organic electronics

Paul H. Wöbkenberg, Goki Eda, Dong Seok Leem, John C. De Mello, Donal D.C. Bradley, Manish Chhowalla, Thomas D. Anthopoulos

Research output: Contribution to journalArticle

79 Citations (Scopus)

Abstract

Interlayer lithography is used to pattern highly conductive, solution-processed, reduced graphene oxide source and drain electrodes down to 10 μm gaps. These patterned electrodes allow for the fabrication of high-performance organic thin-film transistors and complementary circuits. The method offers a viable route towards organic electronics fabricated entirely by solution processing.

Original languageEnglish
Pages (from-to)1558-1562
Number of pages5
JournalAdvanced Materials
Volume23
Issue number13
DOIs
Publication statusPublished - Apr 5 2011

Keywords

  • dielectrics
  • graphene
  • lithography
  • organic semiconductors
  • self-assembled monolayers
  • transistors

ASJC Scopus subject areas

  • Materials Science(all)
  • Mechanics of Materials
  • Mechanical Engineering

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  • Cite this

    Wöbkenberg, P. H., Eda, G., Leem, D. S., De Mello, J. C., Bradley, D. D. C., Chhowalla, M., & Anthopoulos, T. D. (2011). Reduced graphene oxide electrodes for large area organic electronics. Advanced Materials, 23(13), 1558-1562. https://doi.org/10.1002/adma.201004161