Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control

Michael L. Geier, Pradyumna L. Prabhumirashi, Julian J. McMorrow, Weichao Xu, Jung Woo T Seo, Ken Everaerts, Chris H. Kim, Tobin J Marks, Mark C Hersam

Research output: Contribution to journalArticle

66 Citations (Scopus)

Abstract

In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

Original languageEnglish
Pages (from-to)4810-4814
Number of pages5
JournalNano Letters
Volume13
Issue number10
DOIs
Publication statusPublished - 2013

Fingerprint

Carbon Nanotubes
rails
Single-walled carbon nanotubes (SWCN)
Threshold voltage
Voltage control
threshold voltage
logic
Rails
Carbon nanotubes
carbon nanotubes
Logic gates
Metals
Thin film transistors
CMOS
Electric power utilization
transistors
thin films
logic circuits
Logic devices
Logic circuits

Keywords

  • CMOS
  • inverter
  • NAND
  • NOR
  • SWCNT
  • transistor

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Bioengineering
  • Chemistry(all)
  • Materials Science(all)
  • Mechanical Engineering

Cite this

Geier, M. L., Prabhumirashi, P. L., McMorrow, J. J., Xu, W., Seo, J. W. T., Everaerts, K., ... Hersam, M. C. (2013). Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control. Nano Letters, 13(10), 4810-4814. https://doi.org/10.1021/nl402478p

Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control. / Geier, Michael L.; Prabhumirashi, Pradyumna L.; McMorrow, Julian J.; Xu, Weichao; Seo, Jung Woo T; Everaerts, Ken; Kim, Chris H.; Marks, Tobin J; Hersam, Mark C.

In: Nano Letters, Vol. 13, No. 10, 2013, p. 4810-4814.

Research output: Contribution to journalArticle

Geier, ML, Prabhumirashi, PL, McMorrow, JJ, Xu, W, Seo, JWT, Everaerts, K, Kim, CH, Marks, TJ & Hersam, MC 2013, 'Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control', Nano Letters, vol. 13, no. 10, pp. 4810-4814. https://doi.org/10.1021/nl402478p
Geier ML, Prabhumirashi PL, McMorrow JJ, Xu W, Seo JWT, Everaerts K et al. Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control. Nano Letters. 2013;13(10):4810-4814. https://doi.org/10.1021/nl402478p
Geier, Michael L. ; Prabhumirashi, Pradyumna L. ; McMorrow, Julian J. ; Xu, Weichao ; Seo, Jung Woo T ; Everaerts, Ken ; Kim, Chris H. ; Marks, Tobin J ; Hersam, Mark C. / Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control. In: Nano Letters. 2013 ; Vol. 13, No. 10. pp. 4810-4814.
@article{ec2cbd9d5d2149ad81db834a1845dd80,
title = "Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control",
abstract = "In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.",
keywords = "CMOS, inverter, NAND, NOR, SWCNT, transistor",
author = "Geier, {Michael L.} and Prabhumirashi, {Pradyumna L.} and McMorrow, {Julian J.} and Weichao Xu and Seo, {Jung Woo T} and Ken Everaerts and Kim, {Chris H.} and Marks, {Tobin J} and Hersam, {Mark C}",
year = "2013",
doi = "10.1021/nl402478p",
language = "English",
volume = "13",
pages = "4810--4814",
journal = "Nano Letters",
issn = "1530-6984",
publisher = "American Chemical Society",
number = "10",

}

TY - JOUR

T1 - Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control

AU - Geier, Michael L.

AU - Prabhumirashi, Pradyumna L.

AU - McMorrow, Julian J.

AU - Xu, Weichao

AU - Seo, Jung Woo T

AU - Everaerts, Ken

AU - Kim, Chris H.

AU - Marks, Tobin J

AU - Hersam, Mark C

PY - 2013

Y1 - 2013

N2 - In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

AB - In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

KW - CMOS

KW - inverter

KW - NAND

KW - NOR

KW - SWCNT

KW - transistor

UR - http://www.scopus.com/inward/record.url?scp=84885459247&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84885459247&partnerID=8YFLogxK

U2 - 10.1021/nl402478p

DO - 10.1021/nl402478p

M3 - Article

C2 - 24020970

AN - SCOPUS:84885459247

VL - 13

SP - 4810

EP - 4814

JO - Nano Letters

JF - Nano Letters

SN - 1530-6984

IS - 10

ER -