We report on a quantitative study of boron penetration from pH polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O2 or N2O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model (o predict the magnitude of boron penetration, N B , for thicknesses other than those measured. We find that the minimum fox required to inhibit boron penetration is always 2-4 nm less when N2U-grown gate oxides are used in place of U2grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in TJLSI technologies. Because of the strong dependence of boron penetration on tm, incremental variations in oxide thickness result in a large variation in .V, leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10-1 cm-2.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Physics and Astronomy (miscellaneous)