Ultrathin (2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

M. L. Green, E. P. Gusev, R. Degraeve, Eric Garfunkel

Research output: Contribution to journalArticle

683 Citations (Scopus)

Abstract

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal-oxide-semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (2 and Si-O-N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices will be manufactured with SiO2 and Si-O-N for the foreseeable future, continued scaling of integrated circuit devices, essentially the continued adherence to Moore's law, will necessitate the introduction of an alternate gate dielectric once the SiO2 gate dielectric thickness approaches ∼1.2 nm. It is hoped that this article will prove useful to members of the silicon microelectronics community, newcomers to the gate dielectrics field, practitioners in allied fields, and graduate students. Parts of this article have been adapted from earlier articles by the authors [L. Feldman, E. P. Gusev, and E. Garfunkel, in Fundamental Aspects of Ultrathin Dielectrics on Si-based Devices, edited by E. Garfunkel, E. P. Gusev, and A. Y. Vul' (Kluwer, Dordrecht, 1998), p. 1 [Ref. 1]; E. P. Gusev, H. C. Lu, E. Garfunkel, T. Gustafsson, and M. Green, IBM J. Res. Dev. 43, 265 (1999) [Ref. 2]; R. Degraeve, B. Kaczer, and G. Groeseneken, Microelectron. Reliab. 39, 1445 (1999) [Ref. 3].

Original languageEnglish
Pages (from-to)2057-2121
Number of pages65
JournalJournal of Applied Physics
Volume90
Issue number5
DOIs
Publication statusPublished - Sep 1 2001

Fingerprint

microelectronics
silicon
integrated circuits
scaling
oxynitrides
metal oxide semiconductors
students
melting points
field effect transistors
physical properties
electrical properties
electrical resistivity
defects

ASJC Scopus subject areas

  • Physics and Astronomy(all)
  • Physics and Astronomy (miscellaneous)

Cite this

Ultrathin (2 and Si-O-N gate dielectric layers for silicon microelectronics : Understanding the processing, structure, and physical and electrical limits. / Green, M. L.; Gusev, E. P.; Degraeve, R.; Garfunkel, Eric.

In: Journal of Applied Physics, Vol. 90, No. 5, 01.09.2001, p. 2057-2121.

Research output: Contribution to journalArticle

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